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| ? semiconductor components industries, llc, 2015 august, 2015 ? rev. 3 1 publication order number: ncp1339/d ncp1339 high-voltage, quasi- resonant controller featuring valley lock-out and power saving mode the ncp1339 is a highly integr ated quasi?resonant flyback controller capable of controlling rugged and high?performance off?line power supplies as required by adapter applications. with an integrated active x?cap discharge feature and power savings mode, the ncp1339 can enable no?load power consumption below 10 mw for 45 w notebook adapters. the quasi?resonant current?mode flyback stage features a proprietary valley?lockout circuitry, ensuring stable valley switching. this system works down to the 6 th valley and toggles to a frequency foldback mode to eliminate switching losses. when the loop tends to force below 25?khz frequencies, the ncp1339 skips cycles to contain the power delivery. to help build rugged converters, the controller features several key protective features: an internal brown?out, a non?dissipative over power protection for a constant maximum output current regardless of the input voltage, a latched over?voltage protection through a dedicated pin. features ? high?voltage current source for lossless start?up sequence ? x2 capacitors discharge capability ? power savings mode (psm) for extremely low no?load power: ? wide v cc range from 10 v to 28 v ? latching?off 28?v v cc over?v oltage protection ? abnormal overcurrent fault protection for winding short circuit or inductor saturation detection ? integrated high?voltage startup circuit with brown?out detection ? fault input for severe fault conditions, ntc compatible for otp ? circuit latching off in severe fault detection (ovp or otp) ? internal temperature shutdown ? valley switching operation with valley?lockout for noise?free operation ? frequency fold?back for highest performance in standby mode ? 25?khz clamp and skip mode ? timer?based overload protection (latched or auto?recovery options) ? adjustable overpower protection ? 4?ms soft?start timer ? zcd blanking time to ignore leakage ringing at t urn?off: 3 s for c, d and e versions and 0.7 s for f, g or h versions ? these devices are pb?free and are rohs compliant this document contains information on some products that are still under development. on semiconductor reserves the right to change or discontinue these products without notice. soic?14 nb (less pin 13) d suffix case 751an marking diagram www. onsemi.com see detailed ordering and shipping information in the package dimensions section on page 30 of this data sheet. ordering information 1 14 ncp1339xg awlyww 1 14 ncp1339 = specific device code x = c, d, e, f, g or h a = assembly location wl = wafer lot y = year ww = work week g = pb?free package pin connections hv nc nc vcc drv gnd x2 opp zcd fault fb cs rem
ncp1339 www. onsemi.com 2 part number matrix device version overload protection abnormal overcurrent fault zcd blanking time jittering function ncp1339cdr2g ncp1339c autorecovery autorecovery 3 s disabled ncp1339ddr2g ncp1339d latching?off latching?off 3 s disabled ncp1339edr2g ncp1339e latching?off latching?off 3 s enabled NCP1339FDR2G ncp1339f latching?off latching?off 0.7 s enabled ncp1339gdr2g ncp1339g autorecovery autorecovery 0.7 s enabled ncp1339hdr2g ncp1339h autorecovery autorecovery 0.7 s disabled rsense x2 vout l1 n emi filter rem psm_off gnd gnd vaux vcc fb cs 1 2 3 4 5 6 7 9 10 11 12 13 14 8 ncp1339 figure 1. ncp1339 typical application circuit ncp1339 www. onsemi.com 3 pin function description pin number pin name function 1 x2 when the voltage on this pin disappears, the controller ensures the x2?capacitors discharge. 2 rem the part operates when the rem pin is forced lower than a certain level and enters the power savings mode (psm) otherwise. 3 opp a resistive divider from the auxiliary winding to this pin sets the opp compensation level. 4 zcd input to the demagnetization detection comparator for the qr flyback controller. 5 fault the controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds. a pre- cise pull up current source allows direct interface with an ntc thermistor. fault detection triggers a latch. 6 fb feedback input for the qr flyback controller. allows direct connection to an optocoupler. 7 cs input to the cycle?by?cycle current limit comparator for the qr flyback section. 8 gnd ground reference. 9 drv this is the drive pin of the circuit. the drv high?current capability (?0.5 /+0.8 a) makes it suitable to effec- tively drive high gate charge power mosfets. 10 vcc this pin is the positive supply of the ic. the circuit starts to operate when v cc exceeds 15 v and turns off when v cc goes below 9 v (typical values). after start?up, the operating range is 10 v up to 28 v. an ovp comparator monitors this pin and offers a means to latch the converter in fault conditions. 11 nc 12 nc 13 removed for creepage distance. 14 hv this pin provides a charging current during start?up and auto?recovery faults but also a means to efficiently discharge the input x2 capacitors. ncp1339 www. onsemi.com 4 fault latch vfault(ovp) vfault(otp) s r q q bonok ifault(otp) rfault(clamp) vfault(clamp) 5 v cs /kfb leb tcs(leb2) fb ics 5v opp vilim2 vilim1 leb tcs(leb1) + counter count reset overload timer count up count down pwm peak current comparator peak current comparator w/o opp short circuit comparator vfreeze frozen curent comparator ip_flag pwm reset overcurrent csstop drv vopp vopp thermal shutdown auto?restart fault control drv s r q q latch pwm reset overcurrent qr clock clamp vcc zcd + ? vzcd(th) blanking time tzcd(blank) timeout qr logic drv (internal) (internal) qr clock vfb demag hv rem x2 vcc vcc charge x2 capacitor discharge bonok detection line monitoring psm control hv(stop) latch vfb bo_buf fault or psm vcc management and internal reference hv(stop) uvlo vdd circuit reset when vcc ncp1339 www. onsemi.com 6 electrical characteristics (v cc = 12 v, v hv = 120 v, v fault = open, v fb = 3 v, v cs = 0 v, v zcd = 0 v, c vcc = 100 nf , c drv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics conditions symbol min typ max unit startup and supply circuits supply voltage startup threshold minimum operating voltage operating hysteresis transition from i start1 to i start2 dv/dt = 0.1 v/ms v cc increasing v cc decreasing v cc(on) ? v cc(off) v cc increasing, i hv = 650 a v cc(on) v cc(off) v cc(hys) v cc(inhibit) 14.0 8.0 5.8 0.55 15.0 9.0 ? 1.00 16.0 10.0 ? 1.20 v blanking duration after v cc(off) v cc above v cc(reset) t uvlo(blank) 2 ? 15 s startup delay delay from v cc(on) to qr enable t delay(start) ? ? 725 s minimum voltage for current source opera- tion vhv min ? 30 60 v current flowing out of v cc v cc = 0 v ic1 ?0.8 ?0.5 ?0.3 ma current flowing out of v cc pin v cc = v cc(on) ? 0.5 v ic2 ?15 ?10 ?6 ma off?state leakage current v hv = 500 v, v cc = 15 v, v rem = 0 v i leak1 ? ? 25.5 a hv pin leakage current when psm is active v hv = 141 v i leak2 ? ? 11 a hv pin leakage current when psm is active v hv = 325 v i leak3 ? ? 18 a v cc level during a fault v cc(bias) 4.7 5.5 6.3 v supply current before startup, fault or latch flyback in skip switching at 70 khz v cc = v cc(on) ? 0.5 v v fb = 0.35 v c drv open i cc1 i cc2 i cc3 0.05 0.2 1.0 0.10 0.68 1.6 0.50 1.0 3.0 ma v cc overvoltage protection threshold v cc(ovp) 27 28 29 v v cc overvoltage protection delay t delay(vcc_ovp) 22.5 30.0 37.5 s input filter discharge x2 timer disable switch threshold voltage v th_x2 1.0 1.5 2.0 v hysteresis on the x2 pin v th_x2_hyst ? 150 ? mv x2 input clamp voltage v _x2_clamp ? 4 ? v x2 timer duration x2_timer 50 ? 170 ms x2 input leakage current v x2 = 2.5 v i _x2_leak ? ? 0.3 a maximum discharge switch current v cc = 10v i _x2_dis 7 10 14 ma remote input ? power savings mode remote pin voltage below which psm is deactivated v rem increasing v_rem_on 1 1.5 2 v remote pin voltage above which psm is activated v rem decreasing v_rem_off 7.2 8 8.8 v remote input leakage current v_rem = 10 v i_rem_leak ? 20 1000 na remote timer duration rem_timer 50 ? 170 ms resistance of the remote pin internal pull?down switch r_sw_rem 1000 ? 3000 brown out detection brown?out start level hv pin voltage increasing v bo(start) 90 101 110 v system shutdown threshold hv pin voltage decreasing v bo(stop) 84 93 104 v brown?out detection blanking time v hv decreasing, delay from v bo(stop) to drive disable t bo(stop) 30 ? 100 ms gate drive rise time (10?90%) v drv from 10 to 90% t drv(rise) ? 40 80 ns ncp1339 www. onsemi.com 7 electrical characteristics (v cc = 12 v, v hv = 120 v, v fault = open, v fb = 3 v, v cs = 0 v, v zcd = 0 v, c vcc = 100 nf , c drv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol conditions gate drive fall time (90?10%) 90 to 10% of v drv t drv(fall) ? 20 ? ns current capability source sink v drv = 2 v v drv = 10 v i drv(src) i drv(snk) ? ? 500 800 ? ? ma high state voltage v cc = v cc(off) + 0.2 v, r drv = 10 k v cc = 26 v, r drv = 10 k v drv(high1) v drv(high2) 8 10 ? 12 ? 14 v low stage voltage v fault = 4 v v drv(low) ? ? 0.25 v feedback feedback input open voltage v fb(open) 4.48 4.7 5.0 v v fb to internal current setpoint division ratio k fb 3.8 4.0 4.2 ? fb pull up resistor v fb = 0.4 v r fb 17 20 23 k valley thresholds transition from 1 st to 2 nd valley transition from 2 nd to 3 rd valley transition from 3 rd to 4 th valley transition from 4 th to 5 th valley transition from 5 th to 6 th valley transition from 6 th to ff transition from ff to 6 th valley transition from 6 th to 5 th valley transition from 5 th to 4 th valley transition from 4 th to 3 rd valley transition from 3 rd to 2 nd valley transition from 2 nd to 1 st valley v fb decreasing v fb decreasing v fb decreasing v fb decreasing v fb decreasing v fb decreasing v fb increasing v fb increasing v fb increasing v fb increasing v fb increasing v fb increasing v h2d v h3d v h4d v h5d v h6d v hvcod v hvcoi v h6i v h5i v h4i v h3i v h2i 1.316 1.128 1.034 0.940 0.846 0.760 0.900 1.410 1.504 1.598 1.692 1.880 1.400 1.200 1.100 1.000 0.900 0.800 1.000 1.500 1.600 1.700 1.800 2.000 1.484 1.272 1.166 1.060 0.954 0.830 1.060 1.590 1.696 1.802 1.908 2.120 v maximum on time t on(max) 27 32 40 s demagnetization input zcd threshold voltage v zcd decreasing v zcd(th) 35 55 90 mv zcd hysteresis v zcd increasing v zcd(hys) 15 35 55 mv demagnetization propagation delay v zcd step from 4.0 v to ?0.3 v t dem ? 150 250 ns input voltage excursion upper clamp negative clamp i qzcd = 5.0 ma i qzcd = ?2.0 ma v zcd(max) v zcd(min) 12.4 ?0.9 12.7 ?0.7 13 0 v blanking delay after turn?off (c, d and e versions) (f, g and h versions) t zcd(blank) 2 0.5 3 0.7 4 0.9 s timeout after last demagnetization de- tection timeout while in soft?start timeout after soft?start complete t (out1) t (out2) 80 5.1 100 6 120 6.9 s current sense current sense voltage threshold (v ilim1 ) v cs increasing v cs increasing, v opp = 1 v v ilim1a v ilim1b 0.760 0.760 0.800 0.800 0.840 0.840 v cycle by cycle leading edge blanking du- ration minimum on time minus t cs(delay1) t cs(leb1) 220 275 330 ns cycle by cycle current sense propagation delay v cs dv/dt = 1 v/ s, measured from v ilim1 to drv falling edge t cs(delay1) ? 125 175 ns internal peak current setpoint freeze v freeze ? 200 ? mv abnormal overcurrent fault threshold v cs increasing, v fb = 4 v v ilim2 1.125 1.200 1.275 v ncp1339 www. onsemi.com 8 electrical characteristics (v cc = 12 v, v hv = 120 v, v fault = open, v fb = 3 v, v cs = 0 v, v zcd = 0 v, c vcc = 100 nf , c drv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol conditions current sense abnormal overcurrent fault blanking du- ration step v cs 0 v to v ilim2 + 0.5 v to drv falling edge, dv/dt = 10 v/ s t cs(leb2) 90 120 150 ns abnormal overcurrent fault propagation delay step v cs 0 v to v ilim2 + 0.5 v to drv falling edge, dv/dt = 10 v/ s t cs(delay2) ? 125 175 ns set point decrease for v opp = ? 250 mv v cs increasing, v fb = 4 v v opp(max) 27 31.25 33 % overpower protection delay v cs dv/dt = 1 v/ s, measured from v opp(max) to drv falling edge t opp(delay) ? 125 175 ns overpower signal blanking delay t opp(blank) 100 120 200 ns pull?up current source v cs = 1.5 v i cs ?1.5 1.0 ?0.5 a jittering (for e, f and g versions only) frequency of the jittering cs pin source current cs pin being grounded f jit 1.0 1.3 1.6 khz amplitude of the cs source current cs pin being grounded i jit 90 100 110 a hv pin voltage for jittering activation hv pin voltage rising (v in,jit ) h 210 250 290 v hv pin voltage below which the jittering timer activated hv pin voltage falling (v in,jit ) l 185 220 255 v blanking time before jittering disabling v hv < 184 v t jit(blank) 25 40 55 ms fault protection soft?start period (done digitally with 63 steps) measured from 1 st drv pulse to v cs = v ilim1 t sstart 2.8 4.0 5.0 ms flyback overload fault timer v cs = v ilim1 t ovld 120 160 200 ms overvoltage protection (ovp) threshold v fault increasing v fault(ovp) 2.79 3.00 3.21 v delay before fault confirmation used for ovp detection used for otp detection v fault increasing v fault decreasing t delay(fault_ovp) t delay(fault_otp) 20 20 27.5 27.5 35 35 s overtemperature protection (otp) thresh- old (note 5) v fault decreasing v fault(otp_in) 0.395 0.40 0.435 v otp pull?up current source (note 5) v fault = v fault(otp_in) + 0.2 v t j = 110 c i fault(otp) i fault(otp_110) 42.5 ? 45.5 45.5 48.5 ? a fault input clamp voltage v fault = open v fault(clamp) 1.15 1.7 2.25 v fault input clamp series resistor r fault(clamp) 1.32 1.55 1.78 k auto?recovery timer t a?rec_timer 1.1 2 s stand?by management frequency clamp threshold f clamp 23.5 25 27.5 khz skip threshold v fb decreasing v skip 0.35 0.40 0.45 v skip hysteresis v fb increasing v skip(hys) 35 60 85 mv thermal protection thermal shutdown (note 6) t shdn 140 150 170 c thermal shutdown hysteresis (note 6) t shdn(hys) 20 40 60 c thermal shutdown delay (note 6) t delay(tshdn) ? 30.0 ? s 5. ntc with r 110 = 8.8 k (ttc03?474). 6. the value is not subjected to production test ? verified by design/characterization. ncp1339 www. onsemi.com 9 typical characteristics figure 3. v cc(on) vs. junction temperature figure 4. v cc(off) vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 15.20 15.25 15.30 15.35 15.40 15.45 15.50 100 80 60 40 20 0 ?20 ?40 8.70 8.75 8.80 8.85 8.90 figure 5. v cc(inhibit) vs. junction temperature figure 6. ic1 vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 0.6 0.7 0.8 0.9 1.0 1.1 1.2 100 80 60 40 20 0 ?20 ?40 ?0.75 ?0.70 ?0.65 ?0.60 ?0.55 ?0.45 ?0.40 ?0.35 figure 7. ic2 vs. junction temperature figure 8. v cc(bias) vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 ?13 ?12 ?11 ?10 ?9 ?8 ?7 ?6 100 80 60 40 20 0 ?20 ?40 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 v cc(on) (v) v cc(off) (v) v cc(inhibit) (v) ic1 (ma) ic2 (ma) v cc(bias) (v) 120 120 120 120 ?0.50 120 120 ncp1339 www. onsemi.com 10 typical characteristics figure 9. icc1 vs. junction temperature figure 10. icc2 vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 0.20 0.25 0.30 0.35 0.40 0.45 0.50 100 80 60 40 20 0 ?20 ?40 0.60 0.62 0.64 0.66 0.68 0.70 0.72 0.74 figure 11. icc3 vs. junction temperature figure 12. v th_x2 vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 1.55 1.57 1.59 1.61 1.63 1.65 100 80 60 40 20 0 ?20 ?40 1.30 1.35 1.40 1.45 1.55 1.60 1.65 1.70 figure 13. x2_timer vs. junction temperature figure 14. t leb vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 105 107 109 111 113 115 117 119 100 80 60 40 20 0 ?20 ?40 9.5 10.0 10.5 11.0 11.5 12.0 12.5 icc1 (ma) icc2 (ma) icc3 (ma) vth_x2 (v) x2_timer (ms) i_x2_dis (ma) 120 120 120 120 1.50 120 120 ncp1339 www. onsemi.com 11 typical characteristics figure 15. v_rem_on vs. junction temperature figure 16. v_rem_off vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 1.0 1.1 1.3 1.4 1.5 1.7 1.9 2.0 100 80 60 40 20 0 ?20 ?40 7.5 7.6 7.8 7.9 8.0 8.2 8.3 8.5 figure 17. rem_timer vs. junction temperature figure 18. v bo(start) vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 100 105 110 115 120 125 130 100 80 60 40 20 0 ?20 ?40 95 97 99 101 103 105 107 109 figure 19. v bo(stop) vs. junction temperature figure 20. t bo(stop) vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 90 91 92 93 94 95 96 100 80 60 40 20 0 ?20 ?40 53 58 63 68 73 78 83 v_rem_on (v) v_rem_off (v) rem_timer (ms) vbo(start) (v) vbo(stop) (v) tbo(stop) (ms) 120 1.2 1.6 1.8 120 7.7 8.1 8.4 120 120 120 120 ncp1339 www. onsemi.com 12 typical characteristics figure 21. t drv(rise) vs. junction temperature figure 22. t drv(fall) vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 55 60 65 70 75 80 100 80 60 40 20 0 ?20 ?40 15 20 25 30 35 40 figure 23. k fb vs. junction temperature figure 24. r fb vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 3.99 4.00 4.01 4.02 4.03 4.04 4.05 4.06 100 80 60 40 20 0 ?20 ?40 19.0 19.4 19.6 19.8 20.0 20.4 20.8 21.0 figure 25. t on(max) vs. junction temperature figure 26. v zcd(th) vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 30.0 30.5 31.0 31.5 32.0 33.0 33.5 34.0 100 80 60 40 20 0 ?20 ?40 53 54 55 56 57 58 59 60 tdrv(rise) (ns) tdrv(fall) (ns) kfb rfb (k ) ton(max) ( s) vzcd(th) (mv) 120 120 120 120 19.2 20.2 20.6 120 32.5 120 ncp1339 www. onsemi.com 13 typical characteristics figure 27. t zcd(blank) vs. junction temperature figure 28. t (out1) vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 2.50 2.55 2.60 2.65 2.70 2.75 2.80 100 80 60 40 20 0 ?20 ?40 95 96 97 98 99 100 101 102 figure 29. t (out2) vs. junction temperature figure 30. v ilim1a vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 5.9 6.0 6.1 6.2 6.3 6.4 6.5 100 80 60 40 20 0 ?20 ?40 0.800 0.802 0.804 0.806 0.808 0.810 figure 31. t cs(leb1) vs. junction temperature figure 32. t cs(delay1) vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 260 265 270 275 280 290 100 80 60 40 20 0 ?20 ?40 50 52 54 56 58 60 62 64 tzcd(blank) ( s) t(out1) ( s) t(out2) ( s) vilim1a (v) tcs(leb1) (ns) tcs(delay1) (ns) 120 120 120 120 120 120 ncp1339 www. onsemi.com 14 typical characteristics figure 33. v ilim2 vs. junction temperature figure 34. t cs(leb2) vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 1.210 1.215 1.220 1.225 1.230 100 80 60 40 20 0 ?20 ?40 105 107 109 111 113 115 117 119 figure 35. t cs(delay2) vs. junction temperature figure 36. v freeze vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 40 41 42 43 44 45 46 47 100 80 60 40 20 0 ?20 ?40 192 193 194 195 196 197 198 figure 37. t a?rec_timer vs. junction temperature figure 38. v opp(max) vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 2.1 2.2 2.3 2.4 2.5 2.6 2.7 100 80 60 40 20 0 ?20 ?40 28.0 28.5 29.0 29.5 30.5 31.0 31.5 32.0 vilim2 (v) tcs(leb2) (ns) tcs(delay2) (ns) vfreeze (mv) t(autorec) (s) vopp(max) (%) 120 120 120 120 120 120 30.0 ncp1339 www. onsemi.com 15 typical characteristics figure 39. t ovld vs. junction temperature figure 40. v fault(ovp) vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 157 159 161 163 165 167 169 100 80 60 40 20 0 ?20 ?40 3.00 3.05 3.10 3.15 3.20 3.25 3.30 figure 41. v fault(otp_in) vs. junction temperature figure 42. i fault(otp) vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ?20 ?40 0.400 0.405 0.410 0.415 0.420 100 80 60 40 20 0 ?20 ?40 43.5 44.0 44.5 45.0 45.5 46.0 t(ovld) (ms) vfault(ovp) (v) vfault(otp_in) (v) ifault(otp) ( a) 120 120 120 120 ncp1339 www. onsemi.com 16 detailed operating description introduction the ncp1339 implements a standard quasi?resonant current?mode architecture. this component represents the ideal candidate where low part?count and cost ef fectiveness are the key parameters, particularly in low?cost ac?dc adapters, open?frame power supplies etc. the ncp1339 brings all the necessary components normally needed in modern power supply designs, bringing several enhancements such as non?dissipative opp, brown?out protection or sophisticated frequency reduction management for an optimized efficiency over the power range. accounting for the new needs of extremely low standby power requirements, the part includes an automatic x2?capacitor discharge circuitry which can save the power?consuming resistors otherwise needed across the front?end filtering capacitors. the controller is also able to enter power savings mode (psm) that is, a deep sleep mode via its dedicated remote (?rem?) pin. ? high?v oltage start?up: low standby power results cannot be obtained with the classical resistive start?up network. in this part, a high?voltage current?source provides the necessary current at start?up and turns off afterwards. ? internal brown?out protection: the bulk voltage is internally sensed via the high?voltage pin monitoring (pin 14). when v pin14 is too low, the part stops pulsing. no re?start attempt is made until v pin14 recovers its normal range. at that moment, the brown?out comparator sends a general reset to the controller (de?latch occurs) and authorizes to re?start. ? x2?capacitors discharge capability: per iec?950 standard, the time constant of the front?end filter capacitors and their associated discharge resistors must be less than 1 s. this is to avoid electrical stress when users unplug the converter and inadvertently touch the power cord terminals. the circuitry for discharging the x2 capacitors can save the need for discharge resistors, helping to further save power. ? psm control: a dedicated pin allows the ic to enter a deep sleep mode when the rem input pin is brought above a certain level. this option offers an efficient means to operate the adapter in a power savings mode and draw the least input power from the mains in this mode. when the rem is actively pulled down via a dedicated optocoupler, the adapter immediately re?starts. the component that controls psm is then active in normal operation (active?on) and off in psm (wasting no energy). ? quasi?resonant, current?mode operation: qr operation is an efficient mode where the mosfet turns on when its drain?source is at the minimum (valley). however, at light load, the switching frequency tends to get high. the ncp1339 valley lock?out and frequency foldback technique eliminate this drawback so that the efficiency remains at the highest over the power range. ? valley lockout: a continuous flow of pulses is not compatible with no?load/light?load standby power requirements. to excel in this domain, the controller observes the feedback pin voltage (fb) and when it reaches a level of 1.4 v, the circuit enters a valley lockout mode where the circuit skips a valley. if fb further decreases, more valleys are skipped until 6 th valley is reached. ? frequency fold?back: if fb continues declining and reaches 0.8 v, the current setpoint is frozen to v freeze and the circuit regulates by modulating the switching frequency until it reaches 25 khz (typically). ? skip cycle: to avoid acoustic noise, the circuit prevents the switching frequency from decaying below 25 khz. instead, the circuit contains the power delivery by entering skip cycle mode when the system would otherwise need to further lower the switching frequency below 25 khz. ? internal opp (over power protection): by routing a portion of the negative voltage present during the on?time on the auxiliary winding to the opp pin (pin 3), the user has a simple and non?dissipative means to alter the maximum current setpoint as the bulk voltage increases. if the pin is grounded, no opp compensation occurs. ? internal soft?start: a 4?ms soft?start precludes the main power switch from being stressed upon start?up. it is activated whenever a startup sequence occurs including autorecovery hiccup. ? fault input: the ncp1339 includes a dedicated fault input (pin 5). it can be used to sense an overvoltage condition and latch off the controller by pulling up the pin above the upper fault threshold, v fault(ovp) , typically 3.0 v. the controller is also disabled if the fault pin voltage, v fault , is pulled below the lower fault threshold, v fault(otp_in) , typically 0.4 v. the lower threshold is normally used for detecting an overtemperature fault (by the means of an ntc). ? short?circuit/overload protection: short?circuit and especially overload protections are difficult to implement when a strong leakage inductance between auxiliary and power windings affects the transformer (the aux winding level does not properly collapse in presence of an output short). here, every time the internal 0.8?v maximum peak current limit is activated (or less when opp is used), an error flag is asserted and a 160?ms timer begins counting. when the timer has elapsed, the fault is validated. an internal timer keeps the pulses off for 2 s typically which, associated to the 160?ms pulsing re?try period, ensures a duty?cycle in ncp1339 www. onsemi.com 17 fault mode of 10%, independent from the line level. as soon as the fault disappears, the smps resumes operation. please note that some versions (c, g and h) offer an auto?recovery mode as we just described, versions d, e and f do not and latch off in case of a short circuit. hv current source pin the ncp1339 hv circuitry provides three features: ? start?up current source to charge the v cc capacitor at start?up. ? brown?out protection: when the hv pin voltage is below 93 v for the 50?ms blanking time, the ncp1339 stops operating and recovers when the hv pin voltage exceeds 101 v (typical values) ? x2 capacitor discharge: when circuit x2 pin detects that the power supply is no more powered, the start?up current source turns on to discharge the x2 capacitors. because of this last feature, it is firmly recommended to wire it according to figure 43 sketch . the hv pin is not connected to the bulk voltage but directly to the line terminals through diodes (d 1 and d 2 of figure 43). it is further recommended to implement one or two 2.2?k resistors to reduce the noise that can be picked?up by the hv pin. l1 n emi filter vbulk vcc r1 2.2k r2 2.2k d2 d1 d3 c1 1 2 3 4 5 6 7 9 10 11 12 13 14 8 figure 43. two diodes route the full?wave rectified mains to the hv pin start?up sequence: the start?up time of a power supply largely depends on the time necessary to charge the v cc capacitor to the controller v cc start?up threshold (v cc(on) which is 15 v typically). the ncp1339 high?voltage current?source provides the necessary current for a prompt start?up and turns off afterwards. the delivered current (ic1) is reduced to less than 500 a when the v cc voltage is below v cc(inhibit) (1 v typically). this feature reduces the die stress if the v cc pin happens to be accidentally grounded. when v cc exceeds v cc(inhibit), a 10?ma current (ic2) is provided that charges the v cc capacitor. the v cc charging time is then the total of the two following durations: ? charge from 0 v to v cc(inhibit) : t start1 v cc(inhibit) c vcc ic1 (eq. 1) ? charge from v cc(inhibit) to v cc(on) : ncp1339 www. onsemi.com 18 t start2 v cc(on) v cc(inhibit) c vcc ic2 (eq. 2) assuming a 100? f v cc capacitor is selected and replacing ic1, ic2, v cc(inhibit) and v cc(on) by their typical values, it comes: t start1 1v 100 f 500 a 200 ms (eq. 3) t start2 (15 1) 100 f 10 ma 140 ms t start t start1 t start2 340 ms t start1 t start2 figure 44. v cc at start?up is made of two segments given the short?circuit protection implemented on the hv source v cc(inhibit) v cc(on) if the v cc capacitor is first dimensioned to supply the controller for the traditional 5 to 50 ms until the auxiliary winding takes over, no?load standby requirements usually cause it to be larger. the hv start?up current source is then a key feature since it allows keeping short start?up times with large v cc capacitors (the total start?up sequence duration is often required to be less than 1 s). brown?out circuitry for the vast majority of controllers, input line sensing is performed via a resistive network monitoring the bulk voltage or the incoming ac signal. when in the quest of low standby power, the external network adds a consumption burden and deteriorates the standby power performance of the power supply. owing to its proprietary high?voltage technology, on semiconductor now offers onboard line sensing without using an external sensing network. the brown?out thresholds are fixed (101 v line rising, 93 v falling, typically). respectively correponding to about 72 v rms and 66 v rms, these levels are designed to fit most of standard ac?dc converter applications. the simplified internal schematic appears in figure 45 while typical operating waveforms are drawn in figure 46. ncp1339 www. onsemi.com 19 l1 n emi filter vbulk r2 2.2k r1 2.2k d2 d1 rbo_h rbo_l hv gnd bo_ok figure 45. simplified view of the brown?out circuitry when the hv pin voltage drops below the v bo(stop) threshold (93 v typically) for more than the 50?ms blanking time (t bo(stop) ), the brown?out protection trips: the controller stops generating drv pulses and maintains v cc to the 5.5?v v cc(bias) level. this state is maintained by the high?voltage current?source until the input voltage happens to exceed the brown?out upper threshold (v bo(start) that is 101 v typically). at that moment, the controller briefly grounds the v cc capacitor to make a fresh start?up sequence with soft?start. please note that the hv start?up current is not reduced for the time when v cc is below v cc(inhibit) (as it happens when the power supply is first plugged in) not to delay the power supply recovery. if a brown?out event occurs during the v cc capacitor charge phase, the start?up phase is interrupted but the v cc pin is not grounded to make a fresh restart. the start?up resumes as soon as the line recovers (terminating the brown?out sit uation). figure 46. internal circuit implements a 50?ms timeout to accommodate with full?wave rectification ncp1339 www. onsemi.com 20 x2 discharge circuitry the ncp1339 x2 discharge circuitry in figure 47 uses a dedicated pin (x2) together with an external charge pump?based sensing network to detect the presence or the absence of the mains. owing to this simple external source, the x2 circuitry is independent from the rest of the controller that can be fully disabled in the off mode. a 100?ms timeout block makes sure the x2 discharge switch is only activated upon a real mains loss (when the user unplugs the converter) and not when a parasitic ac line dropout occurs. the internal v cc discharge switch is activated once the x2 timer elapses. at that moment, the hv startup current source is enabled and pumps out the energy stored by the x2 capacitors. l1 n emi filter vbulk r2 2.2k r1 2.2k d2 d1 hv x2 r5 c1 d3 c2 r6 d4 x2 capacitor discharge circuitry vcc c3 gnd hv startup figure 47. simplified block diagram of x2 capacitor discharge circuitry an over temperature protection block monitors the junction temperature during the discharge process and avoids thermal runaway, in particular during open/short pins safety tests. please note that the x2 discharge capability is also active during of f?mode but also before the controller actually starts to pulse (e.g. if the user unplugs the converter during the start?up sequence). power savings mode the ncp1339 features a dedicated input (remote pin) that allows the user to activate an ultra?low consumption mode. figure 48 describes the internal arrangement of the remote circuitry. in normal operation, the optocoupler is biased from the secondary side and pulls the remote pin to ground. when the secondary?side circuitry decides to release the optocoupler, the remote pin level starts to grow. it is lifted up by r 1 connected to the auxiliary v cc . c 3 , r 1 and r 2 introduce a time constant that prevents the converter from entering the off mode immediately, in case spurious noise would appear on the opto led bias current. when the voltage across c 2 eventually reaches 8 v, the controller enters the off mode. in the absence of pulses, the auxiliary no longer maintains v cc that slowly vanishes to 0. at this moment, the x2 monitoring circuit is the only living block and the ic power consumption is reduced to an extremely low level. the voltage on the rem pin starts to fall. when it reaches the re?start level (1.5 v), the controller resumes operation and initiates a fresh start?up sequence. if no secondary?side signal appears to bias the optocoupler led, a new self?relaxing cycle takes place when the rem pin voltage reaches 8 v. if a secondary?side signal biases optocoupler before the rem pin voltage has reached 8 v, the power supply operates normally. ncp1339 www. onsemi.com 21 figure 48. simplified block diagram of the remote control input v_rem_off vcc c2 gnd rem to vcc management r2 r1 c3 d2 d1 c1 rem in summary, the rem pin works as follows: ? when pulled below a certain level (v_rem_on, 1.5 v typical), the power supply operates normally. as capacitors are connected to this pin, it is important to discharge them properly during the start?up sequence. a 100?ms timer performs this function by pulling the pin to ground. it is operating in any re?start conditions (brown?out recovery, short?circuit, latch reset and so on) except in the self?relaxing psm mode ( during which the voltage on the pin swings up and down. ? when brought above a certain level (v_rem_off, 8 v typical), the power supply stops working. in the absence of an external bias, the remote pin starts to drop at a pace imposed by the various time constants around it. during this mode, despite the absence of v cc , the x2 discharge circuitry remains active and monitors the ac input line. fault input the ncp1339 includes a dedicated fault input accessible via the fault pin. figure 49 shows the architecture of the fault input. the controller can be latched by pulling up the pin above the upper fault threshold, v fault(ovp) , typically 3.0 v. an active clamp prevents the fault pin voltage from reaching the v fault(ovp) if the pin is open. to reach the upper threshold, the external pull?up current has to be higher than the pull?down capability of the clamp (set by r fault(clamp) at v fault(clamp) ), i.e., approximately 1 ma. this function is typically used to detect a v cc or auxiliary winding overvoltage by means of a zener diode generally in series with a small resistor (see figure 49). neglecting the resistor voltage drop, the ovp threshold is then: v aux(ovp) v z v fault(ovp) , (eq. 4) where vz is the zener diode voltage. the controller can also be latched off if the fault pin voltage, v fault , is pulled below the lower fault threshold, v fault(otp_in) , typically 0.4 v. this capability is normally used for detecting an overtemperature fault by means of an ntc thermistor. a pull up current source i fault(otp) , (typically 45.5 a) generates a voltage drop across the thermistor. the resistance of the ntc thermistor decreases at higher temperatures resulting in a lower voltage across the thermistor. the controller detects a fault once the thermistor voltage drops below v fault(otp_in) . the circuit detects an overtemperature situation when: r ntc i fault(otp) v fault(otp) . (eq. 5) hence, the otp protection trips when r ntc v fault(otp) i fault(otp) (eq. 6) that is 8.8 kohms typically. the controller bias current is reduced during power up by disabling most of the circuit blocks including i fault(otp) . this current source is enabled once v cc reaches v cc(on) . a bypass capacitor is usually connected between the fault and gnd pins. it will take some time for v fault to reach its steady state value once i fault(otp) is enabled. therefore, the lower fault comparator (i.e. overtemperature detection) is ignored during soft?start. ncp1339 www. onsemi.com 22 fault ntc vaux latch vfault(ovp) vfault(otp) s r q q bonok ifault(otp) rfault(clamp) vfault(clamp) 5 v figure 49. fault detection schematic as a matter of fact, the controller operates normally while the fault pin voltage is maintained within the upper and lower fault thresholds. upper and lower fault detector have blanking delays to prevent noise from triggering them. both blanking timers (t delay(fault_ovp) and t delay(fault_otp) ) are typically 27.5 s. when the part is latched?off, the drive is immediately turned off. also, v cc drops and stabilize to the 5.5?v v cc ( bias ) level. the power supply needs to be un?plugged to reset the part as a result of a bonok (bo fault condition) and/or the x2 circuitry activation. psm mode cannot be triggered in latched?off mode. zero current detection the ncp1339 integrates a quasi?resonant (qr) flyback controller. the power switch turn?off of a qr converter is determined by the peak current set by the feedback loop. the switch turn?on is determined by the transformer demagnetization. the demagnetization is detected by monitoring the transformer auxiliary winding voltage. turning on the power switch once the transformer is demagnetized or reset reduces switching losses. once the transformer is demagnetized, the drain voltage starts ringing at a frequency determined by the transformer magnetizing inductance and the drain lump capacitance eventually settling at the input voltage. a qr controller takes advantage of the drain voltage ringing and turns on the power switch at the drain voltage minimum or ?valley? to reduce switching losses and electromagnetic interference (emi). as sketched by figure 50, a valley is detected once the zcd pin voltage falls below the qr flyback demagnetization threshold, v zcd(th) , typically 55 mv. the controller will switch once the valley is detected or increment the valley counter depending on fb voltage. timeout the zcd block actually detects falling edges of the auxiliary winding voltage applied to the zcd pin. at start?up or other transient phases, the zcd comparator may be unable to detect such an event. also, in the case of extremely damped oscillations, the system may not succeed in detecting all the valleys required by vlo operation (see next section). in this condition, the ncp1339 ensures continued operation by incorporating a maximum timeout period that resets when a demagnetization phase is detected. the timeout signal substitutes zcd signal for the valley counter. figure 50 shows the timeout period generator circuit schematic. the steady state timeout period, t (out2) , is set at 6 s. during startup, the output voltage is still low leading to long demagnetization phases difficult to detect since the auxiliary winding voltage is small as well. in this condition, the 6? s steady?state timeout is generally shorter than the inductor demagnetization period and if used to restart a switching cycle, it can cause continuous current mode (ccm) operation for few cycles until the voltage on the zcd pin is high enough for proper valleys detection. a longer timeout period, t (out1) , (typically 100 s) is therefore set during soft?start to prevent ccm operation. in vlo operation, the timeout periods of time are counted instead of valleys when the drain?source voltage oscillations are too damped to be detected. for instance, if the circuit must turn on at the fifth valley and if the zcd ringing only enables to detect: ? valleys 1 to 4: the circuit generates a drv pulse 6 s (steady?state timeout delay) after valley 4 detection. ? valleys 1 to 3: the timeout delay must run twice so that the circuit generates a drv pulse 12 s after valley 3 detection. ncp1339 www. onsemi.com 23 zcd + ? vzcd(th) rzcd czcd drv (internal) blanking time tzcd(blank) timeout qr logic figure 50. valley lockout detection circuitry internal schematic valley lockout (vlo) and frequency foldback (ff) the operating frequency of a traditional qr flyback controller is inversely proportional to the system load. in other words, a load reduction increases the operating frequency. a maximum frequency clamp can be useful to limit the operating frequency range. however such an approach causes instabilities since when this clamp is active, the controller tends to jump (or hesitate) between two valleys generating audible noise. instead, the ncp1339 incorporates a patent pending valley lockout circuitry to eliminate valley jumping. once a valley is selected, the controller stays locked in this valley until the output power changes significantly. this technique extends qr operation over a wider output power range while maintaining good efficiency and limiting the maximum operating frequency. the operating valley (1 st , 2 nd , 3 rd, 4 th , 5 th or 6 th ) is determined by the fb voltage. as v fb decreases or increases, the valley comparators toggle one after another to select the proper valley. the decimal counter increases each time a valley is detected. the activation of an ?n? valley comparator blanks the ?n?1? or ?n+1? valley comparator output depending if v fb decreases or increases, respectively. figure 51 shows a typical frequency characteristic obtainable at low line in a 60?w application. 0 20 40 60 0 210 4 x 410 4 x 610 4 x 810 4 x 110 5 x pout (w) fsw (hz) 1 st 2 nd 3 rd 4 th 5 th 6 th vco mode 1 st 2 nd 3 rd 4 th 5 th 6 th vco mode figure 51. valley lockout frequency vs output power relationship ncp1339 www. onsemi.com 24 when an ?n? valley is asserted by the valley selection circuitry, the controller is locked in this valley until the fb voltage decreases to the lower threshold (?n+1? valley activates) or increases to the ?n valley threshold? + 600 mv (?n?1? valley activates). the regulation loop adjusts the peak current to deliver the necessary output power. each valley selection comparator features a 600?mv hysteresis that helps stabilize operation despite the fb voltage swing produced by regulation loop. valley fb thresholds (typical values): fb falling fb rising 1 st to 2 nd valley 1.4 v ff mode to 6 th valley 1.0 v 2 nd to 3 rd valley 1.2 v 6 th to 5 th valley 1.5 v 3 rd to 4 th valley 1.1 v 5 th to 4 th valley 1.6 v 4 th to 5 th valley 1.0 v 4 th to 3 rd valley 1.7 v 5 th to 6 th valley 0.9 v 3 rd to 2 nd valley 1.8 v 6 th valley to ff mode 0.8 v 2 nd to 1 st valley 2.0 v frequency foldback as the output load decreases (fb voltage decreases), the valleys are incremented from 1 to 6. if when the sixth valley is reached, the fb voltage further decreases below 0.8 v, the controller enters the frequency foldback mode (ff). the current setpoint being internally forced to remain above 0.2 v (setpoint corresponding to v fb = 0.8 v), the controller regulates the power delivery by modulating the switching frequency. when a load increase causes fb to exceed the 1?v ff upper threshold (200?mv hysteresis), the circuit recovers vlo operation. in frequency foldback mode, the system reduces the switching frequency by adding some dead?time after the 6 th valley is detected. this dead?time increases when the fb voltage decays. there is no discontinuity when the system transitions from vlo to ff and the frequency smoothly reduces as fb goes below 0.8 v. the dead?time is dimensioned to generate a 2? s dead?time when v fb = 0.8 v and could linearly go to virtually infinity as v fb falls down to 0.4 v if the switching was not forced to keep above 25?khz to eliminate risk of audible noise. figure 52 summarizes the operation mode with respect to the fb voltage. 25?khz frequency clamp and skip mode as aforementioned, the circuit prevents the switching frequency from dropping below 25 khz. when the switching cycle is longer than 40 s, the circuit forces a new switching cycle. however, the 25?khz frequency clamp cannot generate a drv pulse until the demagnetization is completed. in other words, it cannot cause operation in continuous conduction mode. since the ncp1339 forces a minimum peak current (as aforementioned, the circuit prevents the peak current from dropping below (0.2 v/r sense ) where r sense is the current sense resistor) and a minimum frequency (25 khz typically), the power delivery cannot be continuously controlled down to zero. instead, the circuit stops pulsing when the fb voltage drops below 400 mv and recovers operation when v fb exceeds 450 mv (50?mv hysteresis). this skip?mode method provides an efficient power control in light load. valley 1 3.2 1.6 1.5 1.4 1.1 1.0 0.9 0.8 1.2 v fb (v) fault ! operating mode valley 3 valley 4 valley 5 valley 6 ff valley 2 2.0 1.8 1.7 v fb decreases v fb increases figure 52. valley lockout thresholds ncp1339 www. onsemi.com 25 over power compensation (opp) the power delivered by a qr flyback stage is an increasing function of the bulk voltage, v bulk . it is however desirable to clamp the power delivery to limit the stress on the power components that can otherwise be excessive during transient or fault conditions. an integrated overpower circuit provides a relatively constant output power across bulk voltage, v bulk . practically, the maximum peak current is made a decreasing function of the bulk voltage. the direct measure of the v bulk high?voltage rail would cause losses in the sensing network and hence alter the standby efficiency. instead, the auxiliary winding voltage (v aux ) is used. during power?switch on?time, v aux provides a negative voltage that is a v bulk portion (input voltage scaled down by the primary to auxiliary winding turns ratio) as shown in figure 53. the negative voltage applied to the pin is referred as v opp . the maximum internal current setpoint (v cs(opp) ) is the sum of v opp and peak current sense threshold, v ilim1 . the current setpoint is calculated using equation 7. v cs(opp) v ilim1 v opp (eq. 7) that is that: v cs(opp) v ilim1 n aux n p v bulk (eq. 8) aux bulk p n v n ? ? ? ? figure 53. auxiliary winding voltage waveform ? ? ? v aux (v) for example, (v opp = ?0.25 v) results in a current setpoint of 0.55 v. in general, v opp is selected in the range of ?200 mv at the highest line level. refer to application notes for more details. v cs(opp) 0.8?0.25 0.55 68.75% 0.8 68.75% v ilim1 the opp pin is not designed to operate below ?250 mv which corresponds to a 31.25% decrease of the maximum current limit. if a lower voltage happens to be applied, the internal esd diode that clamps opp pin negative voltages may turn on and lead to carriers injection within the die. to avoid possible resulting disturbance, care must be taken to limit the current sourced by the diode below 2 ma. if the circuitry of figure 54 is used, a conservative condition is: v aux,max r opp1 ?2 ma r opp1 v aux,max 2m (eq. 9) finally, please note that another comparator internally fixes the maximum peak current set point to v ilim1 . hence, even if the opp pin is adversely biased above 0 v, the current setpoint remains clamped to 0.8 v typically. for optimum performance over temperature, we recommend keeping the low?side opp resistor below 3 k . current setpoint as explained in this operating description, the current setpoint is affected by several functions. figure 54 summarizes these interactions. as shown by this figure, the current setpoint is fb/4. however, this value is limited by the following functions: ? this level is clamped during the soft?start phase. the setpoint is actually limited by a clamp level ramping from 0 to 0.8 v within 4 ms. ? it is also limited by the opp function: during the on?time, a negative voltage is applied to the opp pin. this voltage is summed with a 0.8?v voltage reference to form the actual maximum setpoint (see opp section). ncp1339 www. onsemi.com 26 it must be noted that the opp pin voltage is high during the off?time. the summer is designed to face this situation without degradation of the circuitry. ? a minimum setpoint is forced that equals to v freeze (0.2 v, typically). ? in addition, a second ocp comparator ensures that in any case the current setpoint is limited to 0.8 v. this prevents the over?current limit from being increased due to the opp function if a positive voltage is accidentally applied during the on?time. hence, even in this faulty condition, the mosfet current setpoint remains limited to v ilim1 (0.8 v typically). figure 54. current setpoint fb cs rcs rs + ? pwm latch reset 275?ns leb drv opp + ? ocp comp + 0.8 v 3r r minimum setpoint freezing to 0.2 v 0.8 v + ? + ? frozen current + ? soft start ramp opp comp pwm comp 120?ns leb drv + ? short circuit comp 1.2 v overload detection block abnormal over?current fault (csstop) 0.2 v ropp1 rfb vdd current sense and associated protections the feedback voltage (v fb ) is internally divided by k fb (k fb =4, typically) to form the current setpoint. the power switch on time is modulated by comparing a ramp proportional to the switch current to v fb /k fb using the pwm comparator. the switch current is sensed across a current sense resistor, r sense and the resulting voltage is applied to the cs pin. the current sense signal is blanked by a leading edge blanking (leb) circuit. the blanking period eliminates the leading edge spike and high frequency noise during the switch turn?on event. the leb period, t cs(leb1) , is typically 275 ns. the drive pulse terminates once the current sense signal exceeds v fb /k fb . the maximum peak current comparator compares the current sense signal to a reference voltage to limit the maximum peak current of the system. the maximum peak current reference voltage, v ilim1 , is typically 0.8 v. the maximum peak current setpoint is reduced by the overpower compensation (opp) circuitry. in case, a wrong opp signal is applied to the circuit, a second comparator to v ilim1 is placed to get sure that the current setpoint is at least limited to v ilim1. an overload condition causes the output of one of the maximum peak current comparators to transition high and enable the overload timer. figure 55 shows the implementation of the current sensing circuitry. ncp1339 www. onsemi.com 27 cs /kfb leb tcs(leb2) fb ics 5 v opp vilim2 vilim1 leb tcs(leb1) + counter count reset drv csstop vopp overload timer count up count down disable drv pwm comparator peak current comparator with opp peak current comparator w/o opp short circuit comparator vopp figure 55. overload circuitry overload protection the overload timer integrates the duration of the overload fault. that is, the timer count increases while the fault is present and reduces its count once it is removed. the timer counts up or down in 10 ms increments. the overload timer duration, t ovld , is typically 160 ms. if both the pwm and maximum peak current comparators toggle at the same time, the pwm comparator takes precedence and the overload timer counts down. when the overloard timer elapses, the circuit detects an overload condition and ? the controller latches off (versions d, e and f) or ? enters a safe low duty?ratio operation named auto?recovery mode (versions c, g and h). ncp1339 www. onsemi.com 28 latching or auto?recovery mode the ncp1339d, e and f latch off when it detects an overload situation. in this condition, the circuit stops generating drive pulses and let v cc drop down. when v cc has reached its 5.5 v v cc(bias) level, the circuit maintains v cc to this level. it cannot recover operation until v cc drops below its reset level. practically, the power supply must be unplugged to be reset. the ncp1339c, g and h versions are autorecovery. when an overload fault is detected, like latched versions, it stops generating drive pulses and let v cc drop down to its 5.5 v v cc(bias) level. however , the v cc is maintained to its 5.5 v v cc(bias) level for 2 s only (typically). after this 2 s delay time, the circuit attempts to restart. more practically, after an overload condition is detected, operation is interrupted and hence, the v cc that is provided by an auxiliary winding, decays. when it reaches v cc(off) , the circuit waits for 2 s before allowing the circuit operation recovery. during this delay, v cc is forced to the 5.5 v v cc(bias) level so that the blocks monitoring the line remain active. when this phase is complete, a v cc charge sequence starts. figures 56 and 57 show operating waveforms for auto?recovery and latched overload conditions. 2 s figure 56. auto?recovery overload operation figure 57. latched overload operation ncp1339 www. onsemi.com 29 a 2 nd over?current comparator for abnormal overcurrent fault detection a severe fault like a winding short?circuit can cause the switch current to increase very rapidly during the on?time. the current sense signal significantly exceeds v ilim1 . but, because the current sense signal is blanked by the leb circuit during the switch turn on, the power switch current can become huge causing system damage. the ncp1339 protects against this fault by adding an additional comparator for abnormal overcurrent fault detection. the current sense signal is blanked with a shorter leb duration, t cs(leb2) , typically 125 ns, before applying it to the abnormal overcurrent fault comparator. the voltage threshold of the comparator, v ilim2 , typically 1.2 v, is set 50% higher than v ilim1 , to avoid interference with normal operation. four consecutive abnormal overcurrent faults cause the controller to enter latch mode (ncp1339d, e and f versions) or auto?recovery mode (ncp1339c, g and h). the count to 4 provides noise immunity during surge testing. the counter is reset each time a drv pulse occurs without activating the fault overcurrent comparator. protecting from a failure of the current sensing a 1? a (typically) pull?up current source, i cs , pulls up the cs pin to disable the controller if the pin is left open. in addition the maximum on?time (32 s typically) avoids that the mosfet stays permanently on if the switch current cannot reach the current setpoint when for instance, the input voltage is low. soft?start soft?start is achieved by ramping up an internal reference, v sstart , and comparing it to current sense signal. v sstart ramps up from 0 v once the controller powers up. the setpoint rise is then limited by the v sstart ramp so that a gradual increase of the power switch current during start?up. the soft?start duration (that is, the time necessary for the ramp to reach the v ilim1 steady state current limit), t sstart , is typically 4 ms. during soft?start the zcd timeout duration is extended. this is because, during startup, demagnetization phases are long and difficult to detect since the auxiliary winding voltage is small. in this condition, the 6? s steady?state timeout is generally shorter than the inductor demagnetization period and if used to restart a switching cycle, it can cause continuous current mode (ccm) operation for few cycles until the voltage on the zcd pin is high enough for proper valleys detection. a longer timeout period, t (out1) , (typically 100 s) is therefore set during soft?start to prevent ccm operation. also, the fault comparator to 0.4 v (or otp comparator since typically used for overtemperature) is blanked for the soft?start duration. the pin can then be filtered by an external capacitor. jittering capability in order to help meet the emi requirements, the ncp1339 (e, f and g versions) features the jittering capability to average the spectrum rays over the frequency range. the function consists of sourcing a 0 to 100 a, 1.3 khz triangular current out of the cs pin ( i jit ). this current together with the external resistor placed on the cs pin generates an of fset that will change the actual power switch peak current and hence the operation frequency. the jittering current source and hence the jittering function is enabled only in high line condition since at low line, the input voltage ripple is generally sufficient to help meet emi specs. this function is also disabled in frequency foldback operation mode. the jittering function modulates the peak current level. as a result, the fb signal that struggles for compensating this effect and limiting the output voltage ripple, exhibits a swing. the resistor placed between the cs pin and the current sense resistor must not be too high. otherwise, the jittering offset on the cs pin can lead to a fb swing exceeding the vlo mode 600 mv hysteresis inbuilt to avoid unwanted transitions between valleys. in practice, this resistor is generally below 1 kohm. driver the ncp1339 maximum supply voltage, v cc(max) , is 28 v. typical high?voltage mosfets have a maximum gate voltage rating of 20 v. the drv pin incorporates an active voltage clamp to limit the gate voltage on the external mosfets. the drv voltage clamp, v drv(high) is typically 12 v with a maximum limit of 14 v. thermal shutdown an internal thermal shutdown circuit monitors the junction temperature of the ic. the controller is disabled if the junction temperature exceeds the thermal shutdown threshold, t shdn , typically 150 c. a continuous v cc hiccup is initiated after a thermal shutdown fault is detected. the controller restarts at the next v cc(on) once the ic temperature drops below t shdn by the thermal shutdown hysteresis, t shdn(hys) , typically 40 c. the thermal shutdown is also cleared if v cc drops below v cc(reset) , a brown?out fault is detected or if the controller enters power savings mode. a new power up sequences commences at the next v cc(on) once all the faults are removed. ncp1339 www. onsemi.com 30 ordering information part number flyback overload protection abnormal overcurrent fault zcd blanking time jittering function shipping ? ncp1339cdr2g auto-recovery autorecovery 3 s disabled 2500 / tape & reel ncp1339ddr2g latching?off latching?off 3 s disabled ncp1339edr2g latching?off latching?off 3 s enabled NCP1339FDR2G latching?off latching?off 0.7 s enabled ncp1339gdr2g auto-recovery autorecovery 0.7 s enabled ncp1339hdr2g auto-recovery autorecovery 0.7 s disabled ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. ncp1339 www. onsemi.com 31 package dimensions soic?14 nb, less pin 13 case 751an issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of at maximum material condition. 4. dimensions d and e do not include mold protrusions. 5. maximum mold protrusion 0.15 per side. h 14 8 7 1 m 0.25 b m c h x 45 seating plane a1 a m dim min max millimeters d 8.55 8.75 e 3.80 4.00 a 1.35 1.75 b 0.35 0.49 l 0.40 1.25 e 1.27 bsc a3 0.19 0.25 a1 0.10 0.25 m 0 7 h 5.80 6.20 h 0.25 0.50 6.50 13x 0.58 13x 1.18 1.27 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. s a m 0.25 b s c b 13x b a e d e detail a l a3 detail a on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp1339/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative |
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